Multi-chip module connection by way of bridging blocks

ABSTRACT

One aspect provides an integrated circuit (IC) multi-chip packaging assembly, comprising a first IC chip having packaging substrate contacts and bridging block contacts, a second IC chip having packaging substrate contacts and bridging block contacts, and a bridging block partially overlapping the first and second IC chips and having interconnected electrical contacts on opposing ends thereof that contact the bridging block contacts of the first IC chip and the second IC chip to thereby electrically connect the first IC chip to the second chip.

TECHNICAL FIELD

This application is directed to a multi-chip stacking of integrateddevices using partial device overlap.

BACKGROUND

Packaging of multiple semiconductor chips in 2.5D (2.5 dimensional) and3D (3 dimensional) packages is the latest trend in the semiconductorindustry. Current conventional embodiments employ either siliconinterposers in a side by side configuration, termed 2.5D, or by verticalstacking of die with thru-silicon vias (TSV) to achieve true 3D devices,and in many cases both types of technologies are used. TSV is animportant developing technology that utilizes short, vertical electricalconnections or “vias” that pass directly through a silicon wafer inorder to establish an electrical connection from the active side to thebackside of the die, thus providing the shortest interconnect path andcreating an avenue for the ultimate in 3D integration. A siliconinterposer is typically a wide silicon layer on which multiple chips aresurface mounted, either vertically or horizontally, and most oftenemploys TSV to make connections from the package substrate to the chipsbonded thereto. The use of silicon interposers and TSV offer greaterspace efficiencies and higher interconnect densities than wire bondingand general flip chip technology. The combination of these technologiesenables a higher level of functional integration and performance in asmaller form factor in that their presence allows a manufacturer tostack vertically IC devices and pass electrical signals and power andground up and down the through the stack.

SUMMARY

One aspect provides an integrated circuit (IC) multi-chip packagingassembly, comprising a first IC chip having packaging substrate contactsand bridging block contacts, a second IC chip having packaging substratecontacts and bridging block contacts. This embodiment further comprisesa bridging block that partially overlaps the first and second IC chipsand has interconnected electrical contacts on opposing ends thereof thatcontact the bridging block contacts of the first IC chip and the secondIC chip, to thereby electrically connect the first IC chip to the secondchip.

Another embodiment provides an integrated circuit (IC) multi-chippackaging assembly, comprising first and second sub-packagingassemblies. The first sub-packaging assembly comprises a first IC chiphaving packaging substrate contacts and bridging block contacts, and asecond IC chip having packaging substrate contacts and bridging blockcontacts. This embodiment further comprises a bridging block thatpartially overlaps the first and second IC chips and has interconnectedelectrical contacts on opposing ends thereof that contact the bridgingblock contacts of the first IC chip and the second IC chip, to therebyelectrically connect the first IC chip to the second chip. The secondsub-packaging assembly comprises a second substrate having bond padswherein the packaging substrate contacts of the first and second ICchips are connected to the bond pads of the second sub-packagingassembly by bonding contacts. The bridging block has a thickness that isless than a thickness of the bonding contacts and is located between thefirst and second sub-packaging assemblies.

Yet another embodiment provides a method of manufacturing an integratedcircuit (IC) multi-chip packaging assembly. In this embodiment, themethod comprises obtaining a first IC chip having packaging substratecontacts and bridging block contacts, obtaining a second IC chip havingpackaging substrate contacts and bridging block contacts, and obtaininga bridging block comprising interconnected first electrical contactslocated on one end thereof and second electrical contacts located onopposing, second end thereof. The first electrical contacts of thebridging block are bonded to the bridging block contacts of the first ICchip, and the second electrical contacts of the bridging block arebonded to the bridging block contacts of the second IC chip.

BRIEF DESCRIPTION

Reference is now made to the following descriptions taken in conjunctionwith the accompanying drawings, in which:

FIG. 1 illustrates an embodiment of a IC packaging assembly;

FIG. 2 illustrates an embodiment of a bridging block used in the ICpackaging assembly of FIG. 1;

FIG. 3 illustrates another embodiment of the IC packaging assembly ofFIG. 1 that includes using multiple bridging blocks;

FIG. 4 illustrates another embodiment of an IC packaging assemblymultiple IC chips bridged by a bridging block; and

FIG. 5 illustrates another embodiment of the IC packaging assembly ofFIG. 1 bonded to a second IC packaging assembly.

DETAILED DESCRIPTION

The present disclosure is directed to a packaging assembly that utilizesa thin bridging block to electrically connect two or more IC chipstogether to form a multi-chip sub-packaging assembly, which then can bebonded to a base packaging substrate, which in turn can then be bondedto a printed circuit board. This configuration allows directface-to-face chip attachment that eliminates the need for siliconinterposers and TSV to achieve more compact device integration. This isa significant manufacturing advantage over present processes, becausesilicon interposers and TSV introduce complex manufacturing processesand cost adders. Further, the stacking of the die that is associatedwith 3D technologies can impose power and thermal restrictions.Additionally these silicon interposer structures can introduce signaldelay beyond which is tolerable for certain applications. The use of TSValso has implications on layout configurations. The present disclosureeliminates the need for silicon interposers and TSV, while achievingsimilar levels of integration but avoiding the above-mentioned problems.

The partial overlap of the devices present in the embodiments discussedherein provides the advantage of exposing a portion of one or moredevices to a standard package-like configuration and allows for the useof conventional package interconnects. Additionally, the use of a thinconnecting bridging block allows multiple IC devices to beinterconnected without the need for a silicon interposer or TSV, andallows for high speed interconnects to the package, which are wellcharacterized. The embodiments covered by this disclosure also move thedie-to-die connections to an edge placement so as not to interfere withstandard core floor plan arrangements. The on edge placement also allowsfor more of the IC device to be exposed, thereby providing greatersurface area for more direct connectivity. These die-to-dieinterconnects can be done without long redistribution routes, therebyreducing delay concerns. A brief list of Examples of devices in whichthe various embodiments presented by this disclosure may be used includebaseband (DSP), applications, processors, power management, RFtransceiver, or memory for wireless mobile or digital consumer productapplications, where the I/O counts are higher, for example up around750.

FIG. 1 illustrates one embodiment of an IC packaging sub-assembly 100,as provided by this disclosure. This embodiment comprises at least twoIC chips 105 and 110. IC chips 105 and 110 may be memory chips,processor chips, or other similar active devices. Other embodiments, asdiscussed below, provide a configuration that includes more than two ofthe IC chips 105, 110. Neither IC chip 105 nor 110 need employ theabove-discussed interposers nor TSV as means of interconnect. As usedherein and in the claims, a TSV is a vertical electrical connection or“via” passing from the active device side of silicon wafer to thebackside of the silicon wafer. The embodiments provided by thisdisclosure are counter-intuitive to present practices that verticallystack devices directly over one another using silicon interposers andTSV technology.

The IC chips 105, 110 have packaging substrate contacts 115 a, 115 b andbridging block contacts 120 a, 120 b, respectively. As used herein andin the claims, the word “contacts” may be an array of bond pads, copperpillars, or they may be an array of solder bumps having been placed onbond pads. The illustrations discussed herein show embodiments that areeither copper pillars or solder bumps formed on bond pads. However, itshould be understood that other similar bonding technologies may beused. In one embodiment, the bridging block contacts 120 a, 120 b arehigh density contacts. As used herein and in the claims, high densitycontacts are contacts that have at least about 100 contacts/mm². Inanother embodiment, the bridging block contacts 120 a, 120 b have a finepitch that ranges from about 40 microns to about 50 microns as measuredfrom the center points of adjacent contacts.

A bridging block 125 partially overlaps the IC chips 105, 110 andelectrically connects IC chip 105 to IC chip 110 adjacent the edges ofIC chips 105, 110. The bridging block 125 is significantly smaller inall dimensional respects than a conventional silicon interposer that istypically used in a 2.5D assembly, and which spans all of the chips ofthe assembly. In contrast, the bridging block 125 of the presentdisclosure provides contact between the IC chips 105 and 110 by merelyoverlapping the edges of the IC chips 105 and 110 and making contactwith the bridging block contacts 120 a, 120 b that are located adjacentthe edge of each of the IC chips 105 and 110. As generally seen fromFIG. 1, the packaging substrate contacts 115 a, 115 b, which may be bondpads on which either copper pillars solder bumps are formed thereon, aresignificantly larger than the bridging block contacts 120 a, 120 b andare exposed such that they can be used to bond the packagingsub-assembly 100 to another packaging substrate. Thus, the significantlysmaller bridging block 125 allows interconnection between the IC chips105 and 110 without interfering with the bonding process that bondspackaging assemblies together.

FIG. 2 schematically illustrates an embodiment of the bridging block 125of FIG. 1. As seen in this embodiment, the bridging block 125 includesinterconnected electrical contacts 205 a, 205 b located on opposing endsof the bridging block 125, which are interconnected by traces or runners210. The electrical contacts may be bond pads on which solder bumps maybe formed, or they may be copper contact pillars, or may include solderbumps located on the bond pads, or other similar known bondingstructures. In those embodiments where the bridging block contacts 120a, 120 b of IC chips 105 and 110 have high density contacts, theelectrical contacts 205 a, 205 b will also be high density contacts,such that they can correspondingly match with the high density contactsof IC chips 105 and 110. Additionally, in certain embodiments, they willhave the same pitch as the bridging block contacts 120 a, 120 b, asnoted above. The bridging contacts 120 a, 120 b of IC chips 105 and 110and the electrical contacts 205 a, 205 b of bridging block 125 providefor a high capacity data flow between the IC chips 105 and 110.

The bridging block 125 may be comprised of silicon or other materialsused in semiconductor or semiconductor packaging in which or on which,traces and contacts may be formed. In those embodiments that employsilicon, known thinning silicon processes may be used to fabricate thethin bridging block 125. The bridging block 125 allows it to be used inflip-chip package assemblies without interfering with the bonding of theIC sub-packaging assemblies to form the final IC packaging assembly,while providing a high degree of electrical connectivity betweenadjacent IC chips 105 and 110. For example, in one embodiment, thethickness of the bridging block is less than about 60 microns. Thebridging block 125 serves as a data transfer path between the IC chips105 and 110, however, in other embodiments, it may include activecomponents, such as memory.

The bridging block 125 is surface mounted to IC chips 105 and 110.Further, the bridging block 125 does not employ TSVs, which reducesprocessing costs and other cost adders. As such, such devices shouldhave a lower cost piece part compared to a full interposer used of a2.5D assembly. As used herein and in the claims, “free of a TSV” meansthat the bridging block 125 itself to which IC chips 105, 110 areattached does not include a TSV structure.

FIG. 3 illustrates another embodiment 300 of the IC sub-packagingassembly 100 of FIG. 1. In this embodiment, the IC packagingsub-assembly 300 includes multiple bridging blocks 125, as describedabove regarding FIG. 2. In this embodiment, the bridging block contacts120 a, 120 b of the IC chips 105 and 110 are divided into at least firstand second bridge contact groups 305 a, 305 b and 310 a, 310 b, asillustrated. Each of the bridging blocks 125 are electrically connectedto a respective group of bridging block contacts 305 a, 305 b and 310 a,310 b, as shown and in the manner as previously described. It should beunderstood that in other embodiments, additional bridging blocks 125 maybe present, and in such embodiments, there would be a correspondingnumber of bridging block contacts 305 a, 305 b, and 310 a, 310 b presenton each of the IC chips 105 and 110 to which the additional bridgingblocks 125 could be connected. The additional bridging blocks 125provide additional connectivity between the IC chips 105 and 110 toimprove data transfer between them.

FIG. 4 illustrates another embodiment of an IC packaging assembly 400,wherein an alternative embodiment of the sub-packaging assembly 100 ofFIG. 1 is bonded to another conventional sub-packaging substrate 405 toform the packaging assembly 400. This embodiment comprises multiple ICchips 105, 110, and 410 415 and one bridging chip 125 that electricallyconnects the multiple chips, in a way, as previously discussed withrespect to other embodiments. Though the illustrated embodiment 400shows four IC chips 105, 110, 410 and 415, other embodiments includeconfigurations of three, or more than four IC chips. The additional ICchips 410 and 415 that are electrically connected by the bridging chip125 each have respective packaging substrate contacts 410 a, 415 a andbridging block contacts 220 a, 220 b, as discussed with respect toprevious embodiments. As with previous embodiments, the bridging block125 partially overlaps the IC chips 105, 110, 410 and 415, as shown. Inthis embodiment, the electrical contacts 205 a, 205 b of the bridgingblock 125 (FIG. 2) are divided into the same number of groups as ICchips 105, 110, 410 and 415 being connected together. For example, ifthree IC chips are being connected together, then the electricalcontacts 205 a, 205 b, which are interconnected by traces or runners210, will be divided in first, second, and third groups, and if four ICchips are to be interconnected, then four groups will be present, asillustrated, etc. The properties and configuration of all of thecontacts discussed with respect to this embodiment are the same as thosepreviously discussed regarding other embodiments. Further, embodimentsthat include additional bridging chips, as discussed above, could alsobe used, if so desired.

FIG. 5 illustrates one embodiment of an integrated circuit (IC)multi-chip packaging assembly 500. This embodiment includes the ICpackaging assembly 100 of FIG. 1, which in this embodiment, is a firstsub-packaging assembly 505. It should be understood that any of theembodiments discussed above may be included in the embodiment of FIG. 5.Since the packaging assembly 100 and its various embodiments arediscussed above, no further discussion of them will be undertaken here.The assembly 500, however, further includes a second sub-packagingassembly 508 that has a second substrate 510 that includes bond pads 512and underside interconnects 515. As seen in FIG. 5, the firstsub-packaging assembly 505 is bonded to the bond pads 512 of the secondsub-packaging assembly 508 by way of bonding contacts 520, which in theillustrated embodiment are solder bumps, but could also be copperpillars in other embodiments. The bridging block 125 has a thicknessthat is less than a thickness of the bonding contacts 520, and thus itdoes not interfere with the process of bonding the two sub-packagingassemblies 505 and 515 together. As such, inter-chip connectivity isachieved, while maintaining a lower profile and without the need forinterposers or TSV to interconnect the IC chips 105 and 110 together.

A method of manufacturing is evident from the structures shown in FIGS.1-5, which can be constructed using conventional manufacturing andassembly processes. It should be understood that the method offabrication as set forth therein is for illustrative purposes only.Thus, the present disclosure is not limited to just the method discussedherein.

With reference to FIGS. 1-5, the method of manufacturing an integratedcircuit (IC) multi-chip sub-packaging assembly 100, comprises obtainingfirst and second IC chips 105, 110, each having packaging substratecontacts 115 a, 115 b and bridging block contacts 120 a, 120 b. As usedherein and in the claims “obtaining” means either internallymanufacturing the device or acquiring it from a supplier source. Abridging block 125 is also obtained. The bridging block 125 comprisesinterconnected first electrical contacts 205 a located on one endthereof and second electrical contacts 205 b located on an opposing,second end thereof. The first electrical contacts 205 a of the bridgingblock 125 are bonded to the bridging block contacts 115 a of the firstIC chip 105, and the second electrical contacts 205 b of the bridgingblock 125 are bonded to the bridging block contacts 115 a of the secondIC chip 110. Conventional bonding process, such as solder bump or copperpillar bonding processes may be used to form the bonds. Once thebridging block 125 is electrically connected to the IC chips 105 and110, it forms a data transfer path between the IC chip 105 and 110.

In another embodiment, the method may further comprise obtaining atleast a third IC chip 410 having packaging substrate contacts 410 a andbridging block contacts 220 a. Further, the process of bonding furthercomprises bonding the electrical contacts 205 a, 205 b of the bridgingblock 125 to the bridging block contacts 220 a, 220 b of the at leastthird IC chip 410.

In another embodiment, the bridge contacts 120 a, 120 b of each of thefirst and second IC chips 105, 110 are divided into at least first andsecond bridge contact groups 305 a, 305 b and 310 a and 310 b,respectively. In this embodiment, the step of bonding further comprisesbonding electrical contacts of a second bridging block 125 a to thesecond bridge contacts 305 b, 310 b of the first and second IC chips105, 110.

The bridging block contacts 120 a, 120 b of the first and second ICchips 105, 110 and the electrical contacts 205 a, 205 b of the bridgingblock 125 may be high density contacts having at least about 100contacts/mm².

In another embodiment, the method may further include bonding the ICmulti-chip packaging assembly 505 to a second IC packaging assembly 508.In such embodiments, a second substrate 510 has bond pads 512 whereinthe packaging substrate contacts 115 a, 115 b of the first and second ICchips 105, 110 are connected to the bond pads 512 of the secondsub-packaging assembly 508 by bonding contacts 520. The bridging block125 is located between the first and second packaging assemblies and hasa thickness that is less than a thickness of the bonding contacts 520.

Those skilled in the art to which this application relates willappreciate that other and further additions, deletions, substitutionsand modifications may be made to the described embodiments.

What is claimed is:
 1. An integrated circuit (IC) multi-chip packagingassembly, comprising: a first IC chip having packaging substratecontacts and bridging block contacts; a second IC chip having packagingsubstrate contacts and bridging block contacts; and a bridging blockpartially overlapping said first and second IC chips and havinginterconnected electrical contacts on opposing ends thereof that contactsaid bridging block contacts of said first IC chip and said second ICchip to thereby electrically connect said first IC chip to said secondchip.
 2. The IC multi-chip packaging assembly of claim 1, furthercomprising a third IC chip having packaging substrate contacts andbridging block contacts, wherein said bridging block further partiallyoverlaps said third IC chip, said electrical contacts of said bridgingblock being divided into at least first, second, and third groups, andwherein said first group contacts said bridging block contacts of saidfirst IC chip, said second group contacts said bridging block contactsof said second IC chip, and said third group contacts said bridgingblock contacts of said third IC chip to thereby electrically connectsaid third IC chip to said first and second IC chips.
 3. The ICmulti-chip packaging assembly of claim 1, wherein said bridge contactsof each of said first and second IC chips are divided into at leastfirst and second bridge contact groups and said bridging block is afirst bridging block electrically connected to said first bridge contactgroups of said first and second IC chips, and said IC multi-chippackaging assembly further comprising at least a second bridging blockpartially overlapping said first and second IC chips and havingelectrical contacts on opposing ends thereof that contact said secondbridge contact groups of said first and second IC chips.
 4. The ICmulti-chip packaging assembly of claim 1, wherein said bridging blockcontacts of said first and second IC chips and said electrical contactsof said bridging block are high density contacts.
 5. The IC multi-chippackaging assembly of claim 4, wherein said high density contactscomprise at least about 100 contacts/mm².
 6. The IC multi-chip packagingassembly of claim 1, wherein bridging block contacts have a pitch ofabout 40 to 50 microns.
 7. The IC multi-chip packaging assembly of claim1, wherein said bridging block provides a data transfer path betweensaid first IC chip and said second IC chip.
 8. The IC multi-chippackaging assembly of claim 1, wherein said bridging block is free ofthrough silicon vias (TSV).
 9. The IC multi-chip packaging assembly ofclaim 1, wherein said bridging block has a thickness less than about 60microns.
 10. An integrated circuit (IC) multi-chip packaging assembly,comprising: a first sub-packaging assembly, comprising: a first IC chiphaving packaging substrate contacts and bridging block contacts; asecond IC chip having packaging substrate contacts and bridging blockcontacts; and a bridging block partially overlapping said first andsecond IC chips and having interconnected electrical contacts onopposing ends thereof that contact said bridging block contacts of saidfirst IC chip and said second IC chip to thereby electrically connectsaid first IC chip to said second chip; and a second sub-packagingassembly, comprising: a second substrate having bond pads wherein saidpackaging substrate contacts of said first and second IC chips areconnected to said bond pads of said second sub-packaging assembly bybonding contacts, said bridging block having a thickness that is lessthan a thickness of said bonding contacts and located between said firstand second sub-packaging assemblies.
 11. The IC multi-chip packagingassembly of claim 10, wherein said electrical connection structurecomprises solder bumps or copper pillars.
 12. The IC multi-chippackaging assembly of claim 10, wherein said first sub-packagingassembly further comprises a third IC chip having packaging substratecontacts and bridging block contacts, wherein said bridging blockfurther partially overlaps said third IC chip, said electrical contactsof said bridging block being divided into at least first, second, andthird groups, and wherein said first group contacts said bridging blockcontacts of said first IC chip, said second group contacts said bridgingblock contacts of said second IC chip, and said third group contactssaid bridging block contacts of said third IC chip to therebyelectrically connect said third IC chip to said first and second ICchips.
 13. The IC multi-chip packaging assembly of claim 10, whereinsaid bridge contacts of each of said first and second IC chips aredivided into at least first and second bridge contact groups and saidbridging block is a first bridging block electrically connected to saidfirst bridge contact groups of said first and second IC chips, and saidfirst IC multi-chip packaging assembly further comprising at least asecond bridging block partially overlapping said first and second ICchips and having electrical contacts on opposing ends thereof thatcontact said second bridge contact groups of said first and second ICchips.
 14. The IC multi-chip packaging assembly of claim 10, whereinsaid bridging blocks contacts of said first and second IC chips and saidelectrical contacts of said bridging block are high density contacts,wherein said high density contacts comprise at least about 100contacts/mm².
 15. The IC multi-chip packaging assembly of claim 10,wherein said bridging block is free of through silicon vias (TSV).
 16. Amethod of manufacturing an integrated circuit (IC) multi-chip packagingassembly, comprising: obtaining a first IC chip having packagingsubstrate contacts and bridging block contacts; obtaining a second ICchip having packaging substrate contacts and bridging block contacts;obtaining a bridging block comprising interconnected first electricalcontacts located on one end thereof and second electrical contactslocated on opposing, second end thereof; and bonding said firstelectrical contacts of said bridging block to said bridging blockcontacts of said first IC chip and bonding said second electricalcontacts of said bridging block to said bridging block contacts of saidsecond IC chip.
 17. The method of claim 16, further comprising obtainingat least a third IC chip having packaging substrate contacts andbridging block contacts, and said bonding further comprises bonding saidelectrical contacts of said bridging block to said bridging blockcontact of said at least third IC chip.
 18. The method of claim 16,wherein said bridge contacts of each of said first and second IC chipsare divided into at least first and second bridge contact groups andsaid bonding further comprises bonding electrical contacts of a secondbridging block to said second bridge contacts of said first and secondIC chips.
 19. The method of claim 16 wherein said bridging blockscontacts of said first and second IC chips and said electrical contactsof said bridging block are high density contacts having at least about100 contacts/mm².
 20. The method of claim 16 further including bondingsaid IC multi-chip packaging assembly to a second IC packaging assembly,comprising: a second substrate having bond pads wherein said electricalcontacts of said first and second IC chips of said first sub-packagingassembly are connected to said bond pads of said second sub-packagingassembly by bonding contacts, said bridging block having a thicknessthat is less than a thickness of said bonding contacts.